The integration of FET structures, using p-channel transistors (PMOS) and n-channel transistors (NMOS), with bipolar transistors has seen increasing use in recent years. These devices are referred to as BICMOS devices. The use of the bipolar transistors as driving elements for the MOS devices improves the speed characteristics of the overall device. The bipolar transistors are characterized by high transconductance which is well suited for driving capacitive loads.
One disadvantage of integrating an MOS device and a bipolar device in the same circuit is that the steps in fabricating the bipolar device differ somewhat from the steps required to fabricate MOS devices. This may necessitate separate fabrication steps for the bipolar devices and the MOS devices which could result in an overly complex process since numerous thermal cycles would be required. In order to accommodate these two processes, there has been a trend towards combining fabrication steps to form various elements of the two devices.
One of the more important structures in both the bipolar device and the MOS device are the semiconductor junctions which form the emitter and the extrinsic base of the bipolar transistor and the source/drains of the MOS device. With present technology, these structures are formed by implanting impurities into the substrate to provide a relatively thin region of impurities of the proper conductivity type and then the impurities driven down into the substrate with subsequent annealing steps to form a metallurgical junction at a predetermined depth. However, formation of both the MOS device and the bipolar device requires these junctions to be accurately aligned with respect to other structures on the substrate. This alignment becomes somewhat difficult when junctions are formed at different steps in the process and when interceded by thermal cycles.
In view of the above disadvantages, there exists a need for an improved process for forming BICMOS devices wherein the emitter and base junctions in the bipolar device and the source/drain junctions of the MOS devices are fabricated with a minimum number of process steps and are exposed to a minimum number of thermal cycles in the process.